00463nam a22001697a 4500 20180131124433.0 160702b xxu||||| |||| 00| 0 eng d 978-81-317-0633-6 eng 20871 003.3 Yalamanchilli, Sudhakar 4019 Introductory VHDL from simulation to synthisis Sudhakar Yalamanchili Pearson 2006 395p, Diploma Engineering 817 BK 5146 5144 0 0 0 0 REF JRU MAIN SHELF-30-B 2016-07-02 675.00 0 003.3 20871 2016-07-02 00:00:00 2016-07-02 BK 0 0 0 0 CS/IT JRU JRU SHELF-50-F 2016-07-02 675.00 1 003.3 20872 2024-05-31 13:21:53 2024-05-28 2016-07-02 BK